DESCRIPTION OF DUTIES
The Senior FPGA Engineer is responsible for design, implementation, and integration of RTL for LTE and 5GNR radio access points. The FPGA engineer will collaborate with peers across many engineering disciplines on the design of unique programmable logic based wireless solutions. The engineer will participate with hardware, software, and test engineers in bring up, design verification testing (DVT) and end-to-end integration of the final product.
Duties & Responsibilities
- FPGA for high-speed real-time data processing applications
- Proficiency with VHDL and scripting languages.
- Zync Ultrascale SoC or equivalent integrated hard processor with programmable logic device.
- ARM AXI interfaces and DMA
- Model based design tools such as DSP Builder and System Generator
- Multi-gigabit design (10Gb/s Ethernet, JESD204, 10GBASE-R/KR, or similar)
- Clock domain partitioning, timing constraints rules, static timing closure
- Hierarchical test bench design
- Automated vector stimulus input and output vector pass/fail checking
- ChipScope or SignalTap debugger or equivalent methods
- Implementation knowledge in the following signal processing areas is highly desirable, Digital NCO, Quadrature Modulator and Demodulator, channel filtering, AGC and PLL and loop filters
- LTE or 5GNR Layer 1 radio implementation with end-to-end system integration experience is preferred.
- Experience in supporting product development through the entire product lifecycle is highly desirable.
- Demonstrated experience developing and integrating designs in a multi-discipline collaborative engineering environment.
Required Skills & Qualifications
- BSEE degree plus a minimum of 8 years experience or MSEE plus a minimum of 5 years experience in electronic hardware development.
- 5+ years relevant experience in the implementation of high-speed real-time FPGA RTL.